Digital-to-analog converter



May 26, 1970 R. w. TRIPP 3,514,

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INVENTOR ATTORNEYS May 26, 1970 R. w. TRIPP DIGITAL-TO-ANALOG CONVERTER 14 sheets-Sheet 5 Filed June 12, 1967 Robert W. Tripp BY W J .4 TTORNEYS 82 T #5 m 0500 l N c: E w mv 9 PT H So 1 2 6500 58 M 31 b F2 2 2 55 A om v I \z ow 52229; a on 3.50 02:0 A Em U ofiEEam woo w mcmEEam T 32:00 8 k 3 y mm ow 52am Il 9 33 .A k mm \Jrom \z+c+ Nu m c+ dummy M \z+=+ k N- 30 M 6500 A 833: Yv w om ouwzz om E 3 6 v 0E May 26, 1970 R. w. TRIPP DIGITAL-TO-ANALOG CONVERTER l4 Sheets-Sheet 4 Filed June 12, 1967 woo FM tEm m OI

INVENTOR Robert W. Tripp ,JQJM

A IZ SIZNEYS May 26, 1970 R. w. TRIPP DIGITAL-TO-ANALOG CONVERTER l4 Sheets-Sheet 5 Filed June 12, 1967 w wE INVENTOR Roberr W. Tripp BY WWW owl AzTORNEYS May 26, 1970 R. w. TRIPP DIGITAL-TO-ANALOG CONVERTER 14 Sheets-Sheet 6 Filed June 12, 1967 moo flu 2.5.55 #0 sm 2S J w wN new 32:00 sien a:

Oh F INVENTOR Robert W. Tripp r BYMQJ1 M n-ul ATORNEYS R. W. TRIPP May 26, 1970 l4 Sheets-Sheet 7 Filed June 12, 1967 afim 030 /m A 56 k S. mm N0 4: 6 80 3:60 OEEEJW sw wtuw dm n w & K 5 ow 0 t kw Nxh. :5 t l :30 Q05 W #N 8 om mm m OE Roberf W; Tri BY 6 INVENTOR on W, W,

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ATTORNEYS May 26, 1970 R. W. TRIPP DIGITAL-TO-ANALOG CONVERTER Filed June 12. 1967 Clock Counter FIG. 10

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|32 4 Resolver I26 I367 f 2 Tachometer as 1- BOX INVENTOR Robert W. Tripp BYG ATTORNEYS May 26, 1970 R. w. TRIPP 3,514,775

DIGITAL-TO-ANALOG CONVERTER Filed June 12, 1967 F I G l4 Sheets-Sheet 12 Down 0' Ref. b

f [L n [L n c n ILLIILlLfl IL F IL L n [L g [L IL [L h n nn' IllL Ln u U U i INVENTOR A ORNEYS May 26, 1970 R, w, T PP 3,514,775

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2 Cos 6 INVENTOR Robert W. Tripp BY M M MJ LJJM A TORNEYS May 26, 1970 R. w. TRIPP 3,514,775

DIGITAL-TO-ANALOG CONVERTER l4 Sheets-$heet 14 FIG. 17

Filed June 12, 1967 X i,- FIG. 16 Q i;

INVENTOR Robert W. Tripp Q BY m,

ATTORNEYS United States Patent 3,514,775 DIGITAL-TO-ANALOG CONVERTER Robert W. Tripp, New Rochelle, N.Y., assignor to Inductosyn Corporation, Carson City, Nev., a corporation of Nevada Filed June 12, 1967, Ser. No. 645,161 Int. Cl. H03k 13/02 US. Cl. 340--347 24 Claims ABSTRACT OF THE DISCLOSURE Apparatus for converting a digital number n to analog signals representative of trigonometric functions of an angle 0=360n/N degrees. In a cyclic time interval divided into N parts, two trains of pulses are generated, the pulses respectively leading and lagging a reference phase by the angle 0 (or 1r/2i-B). The two pulse trains are summed or are used to operate gating devices to provide rectangular wave signals having pulse widths indicative of sine 0 and/or cosine 0. The first train of pulses is generated upon coincidence of the contents of a counter advancing repetitively through N counts and a register storing the number n. The second train of pulses is generated upon coincidence of the counter contents and the output of a translator which provides, typically, the Ns complement of the register contents.

BACKGROUND OF THE INVENTION Field of the invention The present invention pertains to digital-to-analog converters, and more particularly to apparatus for conversion of a digital number it into an analog voltage or current proportional to a trigonometric function, such as sine or cosine, of an angle 0 defined by the relation n/N =0/2 1r or, obviously, n/N=0/ 360 if 0 is expressed in degrees of are instead of radians. The invention particularly pertains to apparatus of this character in which the analog information takes the form of alternating voltages or currents of fixed phase, the analog information residing in the amplitude of the voltage or current waves.

Description of the prior art It has been heretofore proposed to generate alternating voltages or currents of amplitudes representative of trigonometric functions of angles expressed in digital numbers by means of tapped transformers. Such apparatus is disclosed for example in applicants US. Pat. No. 2,849,668 and No. 2,967,017, which are assigned to the assignee hereof.

SUMMARY OF THE INVENTION In accordance with the invention instead, such voltages or currents are generated by means of pulses and with the help of counting, gating and delay circuits.

BRIEF DESCRIPTION OF THE- DRAWINGS In the accompanying drawings,

FIG. 1 is a vector diagram useful in explaining embodiments of the invention using summing for function generation;

FIG. 2 is a vector diagram useful in explaining embodiments of the invention using gating for function generation;

FIG. 3 is a block diagram of an embodiment of the inventive digital-to-analog converter using gating to convert a digital number n to analog signals representing trigonometric functions of an angle 0=360n/N degrees, where N is a constant;

FIG. 4 is a block diagram of an embodiment of the inventive digital-tO-analog converter wherein analog signals representing trigonometric functions are produced by summing;

FIG. 5 is a block diagram of an embodiment of the invention wherein a signal representing one trigonometric function is produced by gating and a signal representing another trigonometric function is produced by summing;

FIG. 6 is a block diagram of an embodiment of the invention using separate upand down-counters in combination with gating and summing devices to produce sine and cosine signals;

FIG. 7 is a block diagram of an embodiment of the invention using a single up-down counter in combination with gating and summing devices to produce sine and cosine signals;

FIG. 8 is a block diagram of an embodiment of the invention wherein both sine and cosine output signals are derived from the same pair of pulse trains;

FIGS. 9 and 10 are block diagrams showing utilization of the digital-to-analog converter of FIG. 3 in conjunction with a position measuring device in a position control and readout system;

FIG. 11 is an electrical schematic diagram of a digitalto-analog converter corresponding to the embodiment shown in block diagram form in FIG. 8.

FIGS. 12 to 14 are sets of waveforms useful in explaining certain of the embodiments of FIGS. 3 to 11;

FIG. 15 is a vector diagram useful in explaining certain embodiments of the invention employing pulse stretching;

FIG. 16 is a diagram of a translator which may be used in certain embodiments, such as that of FIG. 3;

FIG. 17 is a diagram of another form of translator circuit suitable for use in the invention; and

FIGS. 18 and 19 are respectively diagrams of adding and subtracting circuits, such as may be employed in the embodiment of FIG. 3 among others.

DESCRIPTION OF PREFERRED EMBODIMENTS In Fig. 1 the vectors V1 and V2 represent two sinusoidal oscillations, currents or voltages, of the same frequency and amplitude, leading and lagging a zero reference phase in the cycle by equal angles 6. The vector sum of these two oscillations is clearly seen to be 2 cos 0, assuming the vectors to be of unit amplitude. If V3 and V4 are two similar vectors at the phases arm-+0 and 1r/2-0, their sum is seen to be 2 sin 0. The minus sign, while it must be dealt with, is unimportant.

It can be eliminated by reversal of a pair of conductors in the system.

In accordance with the invention, in one of its aspects, a cycle as indicated by the circle in FIG. 1 is identified with the time interval over which a pulse generator develops a number N of equally spaced pulses. This time interval may be denoted l/F, F being the frequency in cycles per second at which the complete count is repeated. The cycle is accordingly composed of N parts, 1000 for example, and a number n ranging from (I to N therefore defines an angle 0 in degrees of arc according to the relation 0/360=n/N. The vectors V1, V2, V3 and V4 of FIG. 1 therefore occur at the counts n, N --n (or, more simply stated, n), N/4-l-n and N/4n in the cycle of N pulses or counts. The vectors at -N/4n also may be expressed as being at the count of 3N /4-n. The invention provides apparatus which develops separate .trains of pulses at the n and n phases of the cycle, or at the Nl4+n and N/4n phases, or at all four phases. In accordance with one particular aspect of the invention, the pulses of the first pair of pulse trains are vectorially combined, for example in a summing network, to provide a voltage or current cyclical at the frequency F, of fixed phase, and in which the component of F frequency is proportional to cos 0.

The second pair of pulse trains similarly vectorially summed give a similar voltage or current, also of fixed phase, in which the component of F frequency is proportional to sin 0.

Referring now instead to FIG. 2, there is shown a diagram including the same four vectors V1 to V4 as in FIG. 1. In accordance with the invention as depicted in FIG. 2 however, the pulse trains are not summed in pairs. Instead, the pulse trains of each pair are employed to control a gate to which is applied an electric signal of suitable form-a D.C. level, pulses or a sinusoidal carrier for example. The rectangular wave cyclical at the rate F which passes through the gate includes a fundamental component which when suitably phase detected against a signal of F frequency, yields a signal whose amplitude is proportional to sin for the pulse trains V1 and V2 (i.e. those at +n and -n counts). For the pulse trains V3 and V4 at N/4+n and N/4-n counts, this amplitude is proportional to cos 0.

FIG. 3 is a block diagram of an embodiment of the invention which produces from the pulses of frequency NF developed in a pulse generator or clock 2 and from a number n between zero and N, which is stored in a register 4, signals at output channels 6 and 8 representative respectively of the sine and cosine of the angle 0:2arn/N. For this purpose, the circuit of FIG. 3 includes a counter 10 to which the pulses of the clock 2 are continuously supplied. The counter develops a count varying from zero to N-l and then resetting to zero as indicated at waveform a in FIG. 12. The changing count thus existing in the counter is supplied in parallel to four coincidence detection circuits 12, 14, 16 and 18 by means of a channel diagrammatically indicated at 20. The channel 20 in cludes conductors sutficient to present, in the number systern adopted, the state of the count. If for example N: 1000 in decimal numbers and if a binary coded decimal system is adopted for presentation of the count to the coincidence circuits, the channel 20 may include twelve pairs of conductors, four pairs for each of the three decimal digits present in the count.

A number n representative of the angle of which it is desired to generate the sine and cosine is introduced into the register 4 in any suitable manner, manually or from a computer for example. The register presents the number n to coincidence detector 12 via a channel 22 and to a translator 30 via a channel 28, the channels 22 and 28 being of the same nature as the channel 20. At coincidence, which occurs once on each of the cycles of frequency F and at the time of the nth pulse in that cycle, the circuit 12 develops a pulse which is delivered by a line 24 to a gate 26. The symbol +n applied to line 24 indicates that the pulse on that line occurs at the phase In of the cycle 1/ F. Cf. FIGS. 1 and 2.

The count stored in the register 4 is also presented via a channel 28 similar to the channel 22 to a translater 30. The translator is a device which converts the number n into a number which may be either N n or, more conveniently, N n-l. Suitable devices for this purpose are well-known. For translation of n to N-n1, FIG. 16 illustrates apparatus suitable for elfective translation of one digit in the number n when that number is presented to the translator in binary form. FIG. 17 illustrates apparatus for effecting that translation when n is in binary coded decimal form. By operation of the translator 30, an output channel 32 therefrom, which may be similar to the channels 20, 22 and 28, presents to the coincidence circuit 16 the number N-n or Nn-l. The circuit 16 consequently delivers an output pulse to gate 26 over a line 34 when the counter 10 contains the count equal to the number presented to coincidence circuit 16 by translator 30. If the translation is to N nl, the output of coincidence detector 16 is a pulse at the phase -nl, i.e. one pulse earlier than n. This is compensated for by a delay unit 17 inserted in line 34.

The pulses delivered to the gate 26 on the lines 24 and 34 serve respectively to close and to open that gate so that an output signal appears on line 6 during that portion of the cycle l/F between the phases n and +11. The nature of this signal depends upon the signal applied to the input terminal of the gate from a line 36. This input signal may be either a DC. level, or it may be the clock pulses from the clock 2, or it maybe an alternating current voltage of some desired carrier frequency.

Consequently the signal on the line 6 is a gated signal representative of the sine of the angle 0 with 0-=21rn/N radians, as illustrated in FIG. 2 and as explained in conjunction with that figure.

The number n is applied by the channel 22 to an adding device 38 as well as to the coincidence circuit 12 and the number N n1 is similarly applied by the channel 32 to a subtracting circuit 40' as well as to the coincidence circuit 16. The adding and subtracting circuits 38 and 40 are, like the translator 30, passive combinations of logic which serve respectively to add and to subtract to the members presented to them the number N/4. Apparatus of this kind is well-known in the art of digital computers. A simple form of adding circuit operating on binary numbers is shown in FIG. 18 and a similar form of subtracting circuit is shown in FIG. 19.

The adding circuit 38 thus presents to the coincidence circuit 14 on a channel 42, which may be similar to the channel 20, a static number n+N/4. Consequently, once per cycle of the counter 10, at the count +n+N 4, there is delivered to an output line 44 from the circuit 14 a pulse, and this pulse is employed to open a gate 46 receiving at its input on line 36 the same signal as does the gate 26.

The subtracter 40 presents to detector 18 via a channel 41 the number N'n 1N/4 so that at the (Nn-1-N/4)th pulse of the cycle a pulse is delivered by the detector at an output line 48. For brevity, the phase of this pulse is indicated as nl-N/4 adjacent line 48 in FIG. 3. That phase being one pulse too early, a one pulse delay unit 19 is inserted in the line 48 between detector 18 and the gate 46. The pulse on line 48 serves to close the gate 46.

In consequence, the gate 46 is open from the phase +n+N/4 to nN/ 4, and the gate delivers on line 8 a gated signal representative of the cosine of the angle 0, as illustrated in FIG. 2 and as explained in conjunction with that figure.

A reference signal generator 50 in FIG. 3 receives from the counter 10 over a channel 11 the pulses at N/ 4 and 3N/4 phases of the counter cycle and generates therefrom a square wave at the counter cycle frequency, displaced in phase by one quarter of the counter cycle from the counter cycle itself. Pulses at the N/ 4 and 3N/ 4 phases may be derived from the counter in various ways,

the cycle being occupied in resetting 999 to 0. While waveform a is shown as a continuous slant line, the state of the counter varies digitally.

The reference waveform output of generator 50 is shown at waveform b.

Waveform represents the output of the sine gate 26 for 0 and 180 values of the angle where 0=360,lL/N. It likewise represents the output of the cosine gate 46 for 90 and 270 Values of 0. Waveform d similarly represents the output of gate 26 for 0:270 and the output of gate 46 for 0=0. In similar fashion waveform e represents the sine channel output at 0:90 and the cosine channel output at 0:180. Waveform f represents the sine channel output at 0:315 and the cosine channel output at 0:315. Waveform g represents the cosine channel output at 0:45 and the sine channel output at 0:225". Waveform h represents the cosine channel output for 0:135 and the sinechannel output for 0:135", while waveform i represents the cosine channel output for 0:225 and the sine channel output for 6:45.

Phase detection of any one of the signals of waveforms c through i against waveform b will yield a signal whose component of frequency F is of amplitude and polarity proportional to the functions of the angle 0 just recited, for the values of 0 mentioned. Of course, 6 can have any of the values permitted by n. The values selected are for illustration only.

FIGS. 1 and 2 are respectively illustrative of what will hereinafter sometimes be called the summing and gating methods of generating sineor cosine-representative signals. FIG. 3 thus constitutes an embodiment of the invention in which the gating method of FIG. 2 is employed for the development of both sineand cosine-representative signals.

FIG. 4 is a block diagram of another embodiment of the invention which operates by the summing method of FIG. 1 instead of the gating method of FIG. 2. The apparatus of FIG. 4 is the same as that of FIG. 3, except that summing devices 60 and 62 replace the gates 26 and 46 of FIG. 3, the source 36 of a signal to be gated being moreover dispensed with. The summing devices 60 and 62 may be any of various well-known devices, such as summing networks or amplifiers.

The summing device 60 supplies at its output line 64 the vector sum of the pulse trains at the +n and n phases, which sum represents 2 cos (21rn/N) radians. The summing device 62 supplies to its output line 66 the vector sum of the pulse trains at n+N 4 and nN/4 phases, which sum represents 2 sin (21rn/N) radians. FIG. 4 thus constitutes an embodiment employing, for both the sine and cosine channels, the summing method of FIG. 1.

Waveforms j, k, m, n, and 0 in FIG. 12 illustrate, for the same values of n and 0 applying to waveforms 0 through i (pertaining to FIG. 3), the nature of the signals in the sine channel 66 and cosine channel 64 of FIG. 4. In FIG. 12, the letters S and C are abbreviations for sine and cosine, and the degree numbers are those for 0, just as shown opposite the waveforms 0 through i. Waveforms a and b apply to both of FIGS. 3 and 4.

It will be observed that in waveforms k and m, where the two trains of pulses being summed coincide, the resultant is of double amplitude.

The embodiments of FIGS. 3 and 4 employ four coincidence detectors to generate pulses at the +n', n, +n+N/ 4 and n-N/4 phases of the counter cycle. It is possible however to generate both sineand cosine-rep resentative signals form a single pair of the pulse trains, by using the summing method for one function and the gating method for the other. FIG. 5 shows such an embodirnent. It produces at an output channel 6 from a gate 26 a signal of the type represented in waveforms 0 through i of FIG. 12 as applied to the sine function and at the output 64 of a summing device 60 a signal of the type represented in waveforms j through 0 of FIG. 12 as applied to the cosine function.

The devices 26 and 60 of FIG. 5 may, as with other cases of corresponding reference characters throughout the drawing, be identical to the similarly referenced elements of structure in FIGS. 3 and 4. Thus the embodiment of FIG. 5 which operates on the vectors V1 and V2 of FIGS. 1 and 2, employs for the generation of pulses at the +n and n phases the same apparatus as do the embodiments of FIGS. 3 and 4. Because the difference between N n and Nn1 may in practice be negligible, the delay units 17 and 19 of FIGS. 3 and 4 have been omitted in FIG. 5.

It should be noted here that because essentially different methods are used in this embodiment for the generation of the sine and the cosine information that the amplitudes of the resulting signals on lines .6 and 64 are quite different from one another. If the sine and cosine outputs are to be used in a single system, it is desirable to make their scale factors more nearly equal. Apparatus for achieving this result is shown in FIG. 8 and will be discussed resently.

FIG. 6 illustrates another embodiment of the invention in which the output signals are of the same character as those developed in the embodiment of FIG. 5, sinerepresentative rectangular waves being delivered at a line 6 from a gate 26, and cosine-representative superpositions of pulse trains being delivered at a line 64 from a summing device 60. The gate 26 receives an input signal on a line 36 as in the embodiments of FIGS. 3 and 5, and it is controlled by start pulses on line 34 and stop pulses on line 24 which may be the same and which carry the same signals as the similarly numbered lines 34 and 24 in FIGS. 3, 4 and 5. The summing device 60 has in FIG. 6 the same inputs, from lines 24 and 34, as in FIGS. 4 and 5.

For development on lines 24 and 34 of the pulses at the +n and n phases of the counter cycle, the embodiment of FIG. 6 moreover employs coincidence devices 12 and 16 and a register 4 which may be respectively identical with the correspondingly identified elements of structure in FIGS. 3, 4 and 5. The translator 30 of those figures is however omitted in FIG. 6. In place thereof the embodiment of FIG. 6 uses a second counter 15 which counts down instead of up, e.g. from 999 down to 0 and then returns on the next clock pulse to 999. Hence it reaches the positive count it at the time when the counter 10 reaches the count N n. Referring to FIG. 13, waveform a duplicates the waveform a of FIG. 12, and represents the state of counter 10 in FIG. 6 just as it does the state of that counter in FIGS. 3 to 5. Waterform a represents the state of counter 15. The two counters are held in the relative phase indicated, resetting together, by operation of a synchronizing circuit 13.

Waveform b in FIG. 13 has the same shape, meaning and origin as in FIG. 12; it is the output of the reference generator 50 of FIG. 6. The waveforms c and d in FIG. 13 represent respectively the pulse trains on lines 24 and 34 of FIG. 6 and, for that matter, in FIGS. 3, 4 and 5 as well on the assumption that 0:90", i.e. that the count n stored in the register 4 is N 4. The result of combining the pulse trains of waveforms c and d of FIG. 13 in the summing device 60 is represented by waveform e in FIG. 13. This waveform is identical to waveform j in FIG. 12, and it will be observed that it contains no component of frequency F, as required by the fact that cos :0. Waveform f in in FIG. 13, representing the output of gate 26 in FIG. 6 for 0:90, is identical to waveform d in FIG. 12. That is, both show the sine-representative output of gate 26, in any of FIGS. 3, 5 and 6, where 0:90. At the right end of waveform f in FIG. 13 there has been shown the appearance of the output signal from gate 26 on the further assumption that that gate is fed at 36 with pulses of frequency high compared to F.

Waveforms g and h in FIG. 13 show in contrast the pulse trains on lines 24 and 34 where 0:45", and their sum (waveform i in FIG. 13) is seen to be identical with waveform. o in FIG. 12a signal having a component at the F rate whose amplitude is proportional to cos 45.

Waveform j of FIG. 13, representing the gated output of gate 26 in FIG. 6, is seen to be identical with waveform f in FIG. 12, i.e. to represent the sine of 45.

FIG. 7 illustrates still another embodiment employing the same gate 26 and summing device 60 as do FIGS. 5 and 6 to generate sineand cosine-representative signals. This embodiment however employs a counter 70 which, un-. like those previously described, counts from to N and then, instead of resetting, counts back to 0. Its complete cycle thus covers a time interval 2/F. A counter control circuit 72 monitors the state of the counter and causes it to reverse its direction of count, without reset, at 0 and N. The operation of the counter is thus as indicated at waveform a in FIG. 14.

Again in FIG. 7 the register 4 contains the number n determining the angle 0=21rn/N of which sineand cosine-representative signals are to be generated. A coincidence detector 12 detects coincidence between this stored number and the state of counter. Two such coincidences are detected per 2/F cycle of the counter. Distributor 74, operating under control of the counter control 72, directs these alternately to lines 24 and 34. Thus line 24 receives pulses when the counter passes through count n on the way up towards N, and line 34 receives pulses when the counter passes through count n on the way down toward zero. The pulses on lines 24 and 34 are shown at waveforms c and d respectively in FIG. 14. The sum of these, delivered by summing device 60 at line 64, is shown at waveform e in FIG. 14. While it contains a component at the fundamental frequency F/ 2 of waveform a, it contains none at the frequency of interest F, as is appropriate to a signal representative of the cosine of 90.

In FIG. 14, waveform 1 shows the output from gate 26 of FIG. 7 for 0=90, when waveform fis phase detected against the reference Waveform b it will give a maximum output.

The waveforms g, h, i and j of FIG. 14 correspond respectively to waveforms c, d, e and f of that figure, but for 0=45 instead of 90.

It is to be noted that in this embodiment two cycles of the count interval from 0 to N are required to develop one pulse at n phase and one pulse at +11 phase. In other words, the information is developed at half the rate applying to FIGS. 3 to 6. The output signals from gate 26 and summing device 60 of FIG. 7 both contain moreover a component at the frequency F 2. This may however be removed by means of a band-pass filter, passing the component of interest at frequency F and rejecting not only multiples thereof but also the subharmonic of frequency F/Z.

The embodiments of FIGS. 5 and 6 have over those of FIGS. 3 and 4 the advantage that they require only two instead of four coincidence detectors. They have the disadvantage of a large difference in scale factor between the amplitudes of the sine and cosine information developed, one being in the form of a gated signal and the other the sum of two trains of narrow pulses. This difference can be compensated for in various ways, and for many purposes need not be wholly compensated. FIG. 8 illustrates an embodiment of the invention in which, according to a further feature of the invention, the pulses of the pulse trains to be summed are widened or stretched before being summed.

FIG. 8 includes the apparatus shown in FIG. 6 for generating on lines 24 and 34 pulses at the phases +11 and -n. Instead however of summing these two pulse trains in the adding device 60, these pulses are employed to open gates 86 and 88 so as to initiate widened pulses, which are terminated T counts later by signals from delay units 80 and 82 which count a preset number T of clock pulses, starting at the phases +11 and n respectively, before delivering stop signals to those gates.

The result is the formation, on output line 64 from the summing device 60 in FIG. 8, of a signal as shown at waveform n in FIG. 13, drawn on the assumption that T=N/2 and that 0=45. The individual stretched pulse 8 trains deliverd to summing device 60 in FIG. 8 by gates 86 and 88, and replacing the pulse trains g and h of FIG. 13 on lines 24 and 34, are shown in FIG. 13 at waveforms k and m. It is to be noted that when the stretched pulses overlap, the summation of the two waveforms is of double amplitude during the phases of overlap.

Since the center of gravity of the pulses in each of the series being summed for development of the cosine-representative signal has been delayed by T/ 2, the opening and closing signals to the sine-developing gate 26 must be delayed in FIG. 8 by the same amount. For this purpose, the delay units 82 and have additional output terminals which, at a count (in those delay units) of T 2 after beginning of counting there, send pulses to gate 26 which serve reprectively to open and to close that gate.

The operation of the embodiment of FIG. 8 can be further understood by reference to FIG. 15, which is a vector diagram similar to those of FIGS. 1 and 2. In FIG. 15 are shown the vectors V1 and V2 of FIGS. 1 and 2, occurring at phases +11 and -11 determined by the value of the number n stored in the register 4 of FIG. 8. For clarity of the drawing, the number n has been assumed in FIG. 15 to be larger than in FIGS. 1 and 2. The phase n and +n are therefore those of the coincidence pulses on lines 34 and 24 in FIG. 8, and they are hence the phases at which the gates 88 and 86 are opened respectively. These gates each close T counts later, at the phases n+T and i+n +T. The pulses stretched to width T which are delivered by gates 88 and 86 to the summing circuit 60 of FIG. 8 are therefore centered on phase T /2 after n and +n respectively, and are indicated in FIG. 15 by vectors V2 and V1 of greater amplitude than V2 and V1. No attempt has been made to indicate by the amount of lengthening of these vectors the increase in amplitude of the fundamental F frequency component present in the widened pulse trains over that present in the pulses on lines 34 and 24.

The vector sum of V1 and V2 has been drawn in on FIG. 15 and is labeled 2 cos 0. That sum lies along a shifted reference phase indicated 0, T/ 2 clock pulses later than the original reference phase 0. The output of the gate 26, labeled sin 0 in FIG. 15, is centered about the substituted reference phase 0, the gate opening at -n+T/2 and closing at +n+T/2. It will be seen that in FIG. 8 the reference generator 51 includes means to delay the output therefrom by T /2 pulses, consistently with the showing of FIG. 15 just described.

FIGS. 9 and 10 show embodiments of the invention which can be used either to drive the rotor of a resolver generally indicated at 122 to an angular position defined (within an angular cycle of the resolver which may be a fraction of 360) by a number n stored in a register-counter 124, or to develop in the device 124 a count constituting a digital read-out 125 of the instantaneous position of the rotor 120.

The resolver may advantageously be a multi-pole position measuring transformer (either linear or rotary) as marketed under the registered trademark Inductosyn and as described, for example, in US. Pat. No. 2,799,835. Such a resolver includes on one member, advantageously the stator, two windings in space quadrature of the pole cycle of the resolver, as disclosed in detail in that patent. This member is indicated at 121 in FIGS. 9 and 10, and the space quadrature winding thereof are energized with currents conforming to the sineand cosine-representative signals produced in accordance with the invention.

FIGS. 9 and 10 include the apparatus shown in FIG. 3, interconnected with the signal channels and lines of FIG. 3, but with the register-counter 124 replacing in FIGS. 9 and 10 the register 4 of FIG. 3. FIGS. 9 and 10 include, in addition, the resolver 122 already mentioned, stator driver amplifiers 126, a phase detector 128, a servo-amplifier 130, and a servomotor 132, which may be coupled to the movable member 120 of the resolver through a gear box 134. A tachometer 136 is shown providing a control on the gain of amplifier 130.

FIG. 9 also includes a DC. source 140, filters 142 in the sine and cosine signal lines 6 and 8, and a set of ganged switches 150a, 15% and 1500, all of which occupy either the full line position shown therefor, or the phantom position shown therefor. In addition, FIG. 9 includes a switch 152, which is independent of the switch 150, and by means of which the input line 36 to the gates 26 and 46 can be energized, either with clock pulses from the pulse generator 2 or with a direct current voltage from the source 140.

When the switches 150a, 150k and 1500 are in the phantom position shown therefor, the register-counter 124 functions as a register to store a number n applied to it through switch 150 b. The apparatus then functions in the manner described in conjunction with FIG. 3 to develop on the lines 6 and 8 voltages representative of the sine and cosine of the angle 6=21rn/N in the manner hereinabove described in detail. In particular, if the switch 152 connects the line 36 to the source 140, the signals on the lines 6 and 8 will be rectangular waves having the fundamental frequency F. The filters 142 serve to remove harmonics of F. The phase detector 128 then receives the net voltage induced in the winding of the secondary member 120 and it also receives the reference voltage from the generator 50. Its output is then a direct current voltage whose amplitude is proportional to the position error of the member 120 and whose sign indicates the sense of that error. This error voltage operates through the servo loop shown to drive the member 120 to the position at which the error voltage falls to zero.

If the switch 152 is connected instead to the clock 2, the operation of the system is essentially the same. The filters 142 will remove not only harmonics of the F frequency but, obviously, the components at NF (the clock pulse frequency) and harmonics thereof.

When the switches 150a, 15% and 1500 are instead set to the full line position shown for them, the apparatus of FIG. 9 serves to provide in the device 124 a digital signal 125 indication of the position of the movable resolver member 120, however assumed or imposed. The error signal output of the phase detector 128 serves to shift the count in the device 124, by one count per modulation cycle F, until that error voltage goes to zero. It will be seen that switch 150a applies the reference voltage of frequency F to the device 124, thus controlling the change in count in the device 124 to one count per cycle of frequency F.

The apparatus of FIG. 10 performs the same functions as those described in conjunction with FIG. 9. It includes instead of the filters 142 a single filter 160 between the secondary member of the resolver and the phase detector 128, and it also includes an additional phase detector 162 to permit recovery of the modulation at F frequency to which the phase detector 128 is to respond. This is necessary because in the embodiment of FIG. 10 no D.C. source 140 is shown for application to the gates 26 and 46, and because the filter 160, downstream of the resolver having inductively related primary and secondary members, has replaced the filters 142 which in FIG. 9 are upstream of that device. The phase detector 162 consequently receives the clock pulses as a reference for the performance of its phase detection function.

FIG. 11 is a more detailed block diagram of an embodiment of the invention employing the gating method for development of a sine-representative signal and employing the summing method, with pulse stretching, for development of the cosine-representative signal. Thus FIG. 11 shows a system of the character shown in FIG. 8. FIG. 11 also shows application of the apparatus of FIG. 8 to energize the space quadrature primary windings of a position measuring transformer such as a resolver, advantageously of the multi-pole type marketed under the registered trademark Inductosyn. Such multi-pole resolvers are described in U.S. Pat. No. 2,799,835. The system of FIG. 11 will be described on the assumption that 10 F=2 kc. and N=1000, although it is of course not limited thereto. F is again the frequency over whose cycle the count It varies once between the limits 0 and N.

In FIG. 11, a clock 314 generates pulses at the rate of two million per second and delivers them simultaneously to reversible (up-down) counter 315, coincidence detector 316, and controlled gates 317 and 318.

The devices indicated at 317 and 318, and the numerous devices of identical appearance in FIG. 11, are NAND gates. Each of these is a device which will produce a false or zero output level when, and only when, all of its inputs are true, or logic one. It thus gives a logic one output when any or all of its inputs is zero. Logic one may be realized by a positive voltage and logic zero by ground or zero potential.

In FIG. 11, reversible counter 315 comprises three cascaded binary-coded-dccimal (BCD) decade counters programmed in a manner described below to count up and down alternately between zero and one thousand, with a thousand represented in the counter as 000. Each full count is taken as one cycle of the reference frequency F. Thus, counting at clock rate of two megacycles per sec- 0nd, and generating one cycle of the reference frequency for each full count of 1000 different states, the counter generates a reference frequency of two kilocycles per second.

The transition of the most significant (hundreds) digit of counter 315 from a 9 to a zero represents the moment at which the counter has gone from 999 to 000, assuming an upward count. This transition is used to set up/down control flip-flop 319 and to reset reference generator flipflop 320. The flip-flops shown in FIG. 11 are of standard double-rank construction, changing state at the trailing edge of a positive going (zero-to-one) pulse applied to the appropriate input, set or reset. Consequently the nine to zero transition in the hundreds BCD order of counter 315 can be used to set flip-flop 319, the units and tens orders having already gone to zero in generating the carry which causes this transition in the hundreds order.

The two output levels from control flip-flop 319 are used to control the direction of count in counter 315. When flip-flop 319 is in the set condition, counter 315 is directed to count down, and when fiip-flop 319 is in reset, counter 315 counts up. Since the counter is reversed while in the 000 state, the next clock pulse throws it into state 999, and when the most significant digit again leaves the 9 state, this time while counting down, the transition signal causes no change in the states of flip-flops 319 and 320, since they are already in the set and reset states respectively.

Flip-flop 319 receives its reset command from gate 321, which senses the transition of the counter through 001. When reset, flip-flop 319 commands counter 3-15 to count upward, and this takes place when the counter has gone into the 000 state fro-m 001 counting down. When, two clock pulses later, the counter again goes through the 001 state, this time to 002, gate 321 again delivers a reset command. This has no effect, however, since the flip-flop is already in its reset state, and the counter is counting upward.

Thus counter 315 is thus programmed via flipflop 319 to count alternately up and down. The reference signal, at F frequency, is generated by flip-flop 320, which is reset at the turn-around point of counter 315 at each end of its full count excursion. To complete the reference generation, gate 322 delivers a set command to flip-flop 320 each time the counter passes through its 500 midpoint in each direction of count.

Thus flip-flop 320 generates the reference signal whose frequency is one thousandth of the clock rate, by being reset at the transition of counter 315 from 999 to 000 when counting up, being set via gate 322 when the counter goes through its 500 midpoint while counting down, being again reset, this time via gate 321, at the counters transition from 001 to 000 when counting down, being again set via gate 322 as the counter goes through 500, this time while counting up, and this pattern repeats itself continuously.

The number n, expressed in three-digit BCD format for compatibility with counter 315, is entered into set register 323. The ratio of clock to reference frequencies being one-thousand to one, the number n" is the same fraction of a thousand as is of 360.

The twelve bipolar output levels of set register 323 are compared, stage for stage, with the corresponding output levels of counter 315 in coincidence circuit 316, which comprises twelve sets of three NAND gates each and a thirteen-input NAND gate 324 receiving an input from each of those sets and, at its thirteenth input, the pulses from clock 314. One such set of three NAND gates is shown at the dash-line box 302, and contains gates 326, 327 and 328. The gate 328 functions simply as an inverter. When either or both of gates 326 and 327 has a low output level (i.e. all inputs to such gate being high), the input to gate 328 is clamped low.

The bipolar outputs of each stage of counter 315 and register 323 are represented as 1 and O, for the set and reset outputs respectively. When a stage is set into the binary one state, its set or 1 output is high (positive, or True), and its reset or 0 output is low (ground, or False); and conversely, when reset to zero, the 1 output is low and the 0- output is high. Hence, in any of the sets 302, the input to gate 328 will be low when the stages of counter 315 and register 323 which are being compared are in the same state, since under this condition of coincidence either gate 326 or 327 is receiving two high inputs and consequently delivers a low output. On the other hand, when the compared stages do not coincide, both gates 326 and 327 are receiving inputs of a high level on one line and a low level on the other; both gates therefore deliver a high output to gate 328. Since gate 328 simply inverts its input, its output to gate 324 is high when, and only when, the compared stages coincide.

The output of coincidence gate 324 remains at the high level as long as any of its inputs is low. When counter 315 reaches the number n which has been loaded into register 323, all twelve stage-pairs under comparison are in coincidence; the twelve inputs to gate 324 are therefore all high, and the next clock assertion pulse acts as a strobe, causing coincidence pulse 325 to be generated. Using the clock to strobe the gate 324 precludes the possibility of generating a false coincidence signal during the finite propagation time within the counter.

Coincidence pulse 325 is delivered to the switching or steering circuit comprising gates 330 and 331, which are controlled by the bipolar outputs of up/down control flip-flop 319. Gates 330 and 331 thus correspond to the distributor 74 of FIG. 7. When flip-flop 319 is reset, its 0 output is high and its 1 output is low, and counter 315 is programmed to count up. At the same time gate 330 is enabled, and gate 331 is inhibited. Thus when counter 315 reaches the number i while counting up, coincidence pulse 325 is blocked at gate 331 but passed through gate 330. Gate 331 is inhibited because, receiving a low input from the output of flip-flop 319, its output is high whether it receives a low or high input from gate 324. Referring to the output of gate 330 as +11, to denote the coincidence when counting up, this signal is used to set the flip-flop gate 340 whose 1 output then goes high, enabling gate 317 to pass clock pulses, which are inverted and entered into digital delay unit 342.

When counting down, the output levels of flip-flop 319, which is now in the set state, inhibit gate 330 and enable gate 331 to pass coincidence pulse 325 at the phase n. This is used to set flip-flop gate 344, which in turn enables gate 318 to pass clock pulses for inversion and entry into digital delay unit 346.

Thus digital delay units 342 and 346 start to count clock pulses upon generation of the coincidence signals +12 and n respectively. The flip-flop gates 340 and 344 deliver their assertion (positive 1) outputs until they are 12 reset by their respective units 342 and 346, at which time gates 317 and 318 respectively are inhibited, the delay units are cleared of pulses, and all is in readiness for the next cycle.

The operation is the same within both digital delay units. Three cascaded modulo-5 counters, followed by two cascaded binary (or modulo-2) counters are driven at clock rate to a full count of 500; at which point they reset to zero and stop. The stopping action is obtained by using the final carry at 5'00 to reset the flip-flops 340 and 344 which control the input gates 317 and 318 to the delay counters. The counter capacity in each delay unit is developed as 5 5=25, 25 5=125, 2=250, and 250- 2.=500. This particular method of generating the delays for stretching of the cosine-representative pulses at phases +11 and -n affords a final carry at time T=500, and also provides a convenient output at time T/2=250= in the form of the carry output from the first of the two binary stages.

The carry outputs at T/2=250 from delay units 342 and 346 respectively are used to set and reset flip-flop gate 350, for development of the sine-representative signal. These carry outputs are 2n counts apartthe spacing in time from n to +ri in FIG. 2.

Since it is necessary to delay the reference signalby a quarter cycle in order to obtain correct phase demodulation of the sine and cosine terms; and since any phase shift of the resultant sine and cosine vectors introduced by the delays must be added to that quarter-cycle delay of the reference term, in order to eliminate phase sensitivity (a basic objective of the invention); then it is clear that by shifting the resultant sine and cosine vectors by a quarter cycle, the additional quarter-cycle delay imposed upon the reference term brings its total delay to exactly a half cycle, which is equivalent to a complete phase reversal, and can be effected without the need for a third delaying network. Since the 0 and 1 outputs of flip-flop 320 are exactly 180 of the reference cycle out of phase with each other, that proper phasing of the reference signal is merely a matter of selecting the proper output line.

In FIG. 11, there is diagrammatically shown at 352 the member of a linear or rotary resolver (such as that of the type described in US. Pat. No. 2,799,835), having thereon two windings 354 and 356 in space quadrature of the pole cycle of the resolver. This member may conveniently be the stationary member of the resolver. These windings are, for the position of switch 351 shown in full lines, driven from a supply E via controlled switches 332 and 333 for the sine term and 334, 335 and 336 for the cosine terms. Switch operation is controlled by an input logic level; a high input closes the switch, a low input opens it. During the assertion (set) output of flip-flop 350, when the 1 output is high, switch 332 connects the winding 354 to E and switch 333 is open. During the period that flip-flop gate 350 is reset, the 0 and 1 outputs open switch 332 and close switch 333, connecting the sine winding 354 to ground.

The combination of gates 367 through 370 constitutes the summing. network for the cosine pulse trains. The outputs of flip-flop gates 340 and 344 are used to control the summing gates 367 through 370 in the following manner.

Gates 367 and 368 constitute 'an exclusive OR gate for the assertion (set) outputs of flip-flop gates 340 and 344; that is, their paralleled output is high Whenever there is an assertion output from either gate 340 or gate 344. If both assertions are present, or neither, the output line is low. The output line from gates 367 and 368 controls switch 334, which connects the cosine stator winding 356 to a value of one-half E The sine term is K sin 0, and the cosine term is 2K cos 0. Driving the sine winding with E and driving the cosine winding with one-half E, for each of the two cosine terms brings the two final terms into scale equality.

During those periods where both gates 340 and 344 are in simultaneous assertion (corresponding to the overlap illustrated at waveform n of FIG. 13), gate 369 

